# Welcome to Project Trellis

Project Trellis documents the Lattice ECP5 architecture (and other related parts) to enable development of open-source tools. Our goal is to provide sufficient information to develop a free and open Verilog to bitstream toolchain for these devices.

Lattice ECP5 Architecture

- Overview
- Tiles
  - Logic Tiles
  - Common Interconnect Blocks (CIBs)
  - IO Tiles
  - Global Clock Tiles
  - Embedded Block RAM (EBR)
  - DSP Tiles
  - System and Config Tiles
- General Routing
- Global Routing
  - Mid Muxes
  - Centre Muxes
  - Spine Tiles
  - TAP_DRIVE Tiles
  - Non-Clock Global Usage
- Bitstream format
  - Basic Structure
  - Control Commands
  - Configuration Data
  - Compression Algorithm
  - Partial Bitstreams
  - Device-Specific Information
- Glossary

Database Development Process

- Database Development Overview
  - NCL Files
  - Fuzzers

libtrellis Documenation

- libtrellis Overview
- Textual Configuration Format

DSP Support

- DSP Support